1. Field of the Invention
Example embodiments of the present invention relate, in general, to a shared contact structure, a semiconductor device and a method of fabricating the semiconductor device.
2. Description of the Related Art
As electronic products are becoming thinner, more lightweight and compact, various research has been conducted in an effort to enhance the performance of semiconductor devices. A semiconductor device, for example, a Static Random Access Memory (SRAM) has generally low power consumption and fast operating speed, as compared to a Dynamic RAM (DRAM). SRAM is widely used as an embedded memory in a central processing unit (CPU), for example.
A unit cell of the SRAM is classified into two primary types: a high load resistor SRAM cell, which employs a high load resistor as a load device, and a complementary metal oxide semiconductor (CMOS) SRAM cell, which employs a P-channel MOS (PMOS) transistor as a load device. The CMOS SRAM cell generally has a plurality of transistors and a pair of nodes. A technique using a shared contact structure is employed to effectively arrange the nodes.
FIGS. 1 to 3 are cross-sectional views illustrating a method of fabricating a conventional shared contact structure. Referring to FIG. 1, the conventional shared contact structure has an isolation layer 13 defining an active region 12 within a semiconductor substrate 11. A gate electrode 19 is formed to cross over the active region 12. The gate electrode 19 has a gate pattern 17 and a gate silicide layer 18 which are sequentially stacked. The gate electrode 19 crosses over the active region 12 and covers a given region of the isolation layer 13. A gate dielectric 15 is interposed between the gate electrode 19 and the active region 12. Spacers 25 are formed on sidewalls of the gate electrode 19. The spacer 25 is composed of an oxide pattern 23 and a nitride pattern 24 which are sequentially stacked. A source/drain extension 21 is formed in the active region 12 below the spacer 25. A source/drain region 29 is formed in the active region 12 adjacent to the gate electrode 19. The source/drain extension 21 is in contact with the source/drain region 29. The source/drain region 29 is composed of a highly doped drain region 27 and a source/drain silicide layer 28 which are sequentially stacked. The semiconductor substrate 11 with gate electrode 19 and the source/drain region 29 is covered by an etch stop layer 31 and an inter-layer dielectric (ILD) 33 which are sequentially stacked. A nitride layer having an etch selectivity with respect to the ILD 33 is used as the etch stop layer 31.
Subsequently, a contact hole 35 is formed through the ILD 33 to form a shared contact structure. The etch stop layer 31 is exposed on a bottom surface of the contact hole 35.
Referring to FIG. 2, the exposed etch stop layer 31 is removed to form an extended contact hole 35′. An upper region of the gate electrode 19 is partially exposed within the extended contact hole 35′, and a top surface of the source/drain region 29 is also partially exposed. In this case, when the etch stop layer 31 remains on the exposed surfaces of the gate electrode 19 and the source/drain region 29, there occurs an increase in contact resistance. Accordingly, the process of removing the etch stop layer 31 must have a sufficient process margin. That is, the process of forming the extended contact hole 35′ includes a process of over-etching the etch stop layer 31. Accordingly, the spacer 25 is etched while the etch stop layer 31 is being removed, so that a top surface of the source/drain extension 21 is partially exposed. In addition, an oxide layer (e.g., a natural oxide layer) remains on the exposed surfaces of the gate electrode 19 and the source/drain region 29. This oxide layer causes an increase in contact resistance. The oxide layer is removed by a wet cleaning process or dry etching process. While the oxide layer is being removed, the surface of the source/drain extension 21 is partially etched by the wet cleaning or dry etching process. That is, an extended hole 35E is formed in a contact region between the source/drain extension 21 and the source/drain region 29, as shown in FIG. 2.
Referring to FIG. 3, a shared contact plug 39 is formed to fill the extended contact hole 35′. The shared contact plug 39 is formed by sequentially stacking a barrier metal layer 37 and a conductive layer 38. As a result, the shared contact plug 39 is in contact with the source/drain region 29 and the gate electrode 19.
However, while the shared contact plug 39 is being formed, the extended hole 35E (see FIG. 2) is also filled with the barrier metal layer 38 to form a plug extension 37E. The plug extension 37E forms a leakage current path between the shared contact plug 39 and the active region 12.